Finite state machines (FSMs) and their outputs are often in the critical timing paths of circuit designs. Optimization of FSMs in synthesis may result in significant reductions in timing delays. Presently, optimization of FSMs focuses on decreasing the delay in the logic that calculates the current state. Though the decrease in delay of an FSM timing to current state may improve the maximum frequency (Fmax) attainable by the FSM, the Fmax attainable by the overall system may not be improved. This is often because the delay from the FSM to downstream registers and/or output terminals is the worst case timing path. Presently, designers hand code state machines in hardware description language (HDL) and arrange the logic to decrease the delay from the FSM to downstream registers and/or output terminals. If after implementing the design specified by the HDL description, the system cannot attain the desired Fmax, achieving the desired Fmax may require changing the HDL description and recompiling, which may be painstaking and prone to errors.